The present disclosure relates to a delay latch circuit and a delay flip-flop. More particularly, the disclosure relates to a delay latch circuit and a delay flip-flop that may be used under low voltage conditions.
Heretofore, sequential circuits have used D (delay) latch circuits and D flip-flops as circuits that hold a state each. These D latch circuits and D flip-flops may employ wired OR (logical add) circuits. The wired OR circuit is a circuit that provides the OR logic by connecting a plurality of outputs in parallel. For example, consider a D latch circuit or a D flip-flop circuit that holds bit information using an inverter loop. A wired OR circuit is formed when two inverters constituting the inverter loop are wired parallelly to a suitable gate terminal that inputs data to the inverter loop. While circuits in the recent years have tended to be required to operate under low voltage conditions, the wired OR circuit has been known to malfunction from time to time at low voltage (e.g., see H. Kaul, et al., “A 300 mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 65 nm CMOS,” ISSCC Dig. of Tech. Papers, pp. 260-261, February 2009, hereinafter referred to as Non-Patent Document 1). Specifically, the ratio of a current Ion flowing in the on-state to a current Ioff flowing in the off-state (Ion/Ioff) generally drops as the voltage is lowered. The drop in the Ion/Ioff ratio can generate contention between the drive current and leak current in the wired OR circuit. The contention thus generated prevents the inverter loop from holding its correct information, causing the circuit to malfunction.
In order to forestall such malfunction under low voltage conditions, a D latch circuit having four two-input NAND (negative AND) gates and a D flip-flop having a two-stage latch circuit structure have been proposed (e.g., see Takashi Minamidani, “Basics of Logic Circuits” (in Japanese), Saiensu-sha, May 2009, p. 124, hereinafter referred to as Non-Patent Document 2). This latch circuit is furnished with two cross-connected NAND gates and two NAND gates that input data to the cross-connected NAND gates. In this structure, wired OR circuits are not used in the D latch circuit and D flip-flop so that current contention will not develop at a reduced Ion/Ioff ratio. This prevents the malfunction of D latch circuits and D flip-flops under low voltage conditions.